This invention relates, in general, to semiconductor devices, and more particularly, to a process of fabricating a semiconductor structure for high power integrated circuits.
High power integrated circuits having both low voltage and power transistors, such as logic or analog circuits and power MOSFETs or bipolar transistors, can be fabricated by isolating regions in a semiconductor epitaxial layer on a substrate. Presently, techniques for isolating the logic devices from the power device include buried layer structures and etch refill structures. A buried layer structure disclosed in Japanese Patent Publication No. 61-285750, published on Dec. 16, 1986, comprises an N.sup.+ type substrate in which an N.sup.+ patterned buried layer is formed. A P-type epitaxial is grown on the substrate, in which a second N.sup.+ patterned buried layer is then formed. An N-type epitaxial layer is formed on the P-type epitaxial layer. In the N-type epitaxial layer, P.sup.+ patterned isolation regions are formed surrounding the buried layer and diffused down to the P-type epitaxial layer. The isolated region over the N.sup.+ buried layer is where the power device is formed, and the isolated region over the P-type epitaxial layer is where the logic devices are formed. A third N.sup.+ patterned buried layer is also formed below the logic device area. The third N.sup.+ buried layer must be formed separately from the second N.sup.+ buried layer because the diffusion depth of the third N.sup.+ buried layer must be kept low in order not to destroy the isolation. This buried layer structure is undesirable because the parasitic NPN transistor formed under the logic device area has a tendency to turn on at low voltage. To reduce the effect of the parasitic NPN transistor, the thickness or the doping concentration of the P-type epitaxial layer, the base of the parasitic NPN transistor, can be increased. An increase in the thickness or the doping concentration of a base of an NPN transistor makes a poor transistor, which is desirable in this case. However, in the buried layer structure of the prior art, the thickness of the P-type epitaxial layer can not be increased more than the length of the vertical diffusion of the N.sup.+ buried layer. This is because the N.sup.+ buried layer must make contact with the N.sup.+ substrate and the N-type epitaxial layer. In addition, if the P-type epitaxial layer has a high doping concentration, the resistivity of the N-type epitaxial layer is difficult to control due to autodoping.
An etch refill structure consists of an N.sup.+ substrate layer that has been etched to form wells therein. Subsequently, a P-type epitaxial layer is formed on the surface and in the wells of the N.sup.+ substrate. The structure is then ground and polished, such that the P-type epitaxial layer is left only in the wells of the N.sup.+ substrate. Then, an N type epitaxial layer is formed on the surface of the substrate and the P-type epitaxial layer. P.sup.+ patterned isolation regions are formed in the N-type epitaxial layer surrounding the N.sup.+ substrate and diffused down to the P-type epitaxial layer. The power and logic devices are built in the same manner as in the buried layer structure. The etch refill structure may be undesirable if polishing equipment is not readily available. Therefore, it would be desirable to provide a semiconductor structure which will reduce the NPN parasitic transistor effect which can be easily fabricated at a low cost, and provide for better device performance.
Accordingly, it is an object of the present invention to provide a semiconductor structure for high power integrated circuits which reduces the NPN parasitic transistor effect.
Another object of the present invention is to provide a semiconductor structure for high power integrated circuits which can be easily fabricated at a low cost and better manufacturability.
An additional object of the present invention is to provide a semiconductor structure which provides for better device performance of high power integrated circuits.